The density of dynamic random access memories (hereinafter, referred to as DRAMS) used as a main memory device in computer systems, have increased about four-fold every three years, and efforts to develop is high speed operation and lower power consumption. High speed operation is desired to reduce the operating speed gap between a central processing unit CPU and the DRAM, and lower power consumption is especially desired in portable devices. DRAMS intended to achieve the high speed operation include synchronous DRAMS using a system clock and a rambus DRAM, while DRAMS intended to achieve the lower power operation includes low power DRAMs aiming at efficient battery operation. The technical art on the rambus DRAM is disclosed in pages 66 to 67 of a paper "symposium on VLSI circuits digest of technical papers 1992" written by N. kushiyama, et at., entitled "500 Mbyte/sec data-rate 512 Kbits.times.9 DRAM using a novel I/O interface". And a conventional synchronous DRAM is disclosed in pages 65 to 66 of a paper "symposium on VLSI circuits digest of technical papers 1993" written by yun-ho CHOI, et al., entitled "16 Mbit synchronous DRAM with 125 Mbyte/sec data rate". A conventional lower power DRAM is disclosed in pages 1112 to 1116 of a paper "IEEE journal of solid-state circuits, vol.25, Oct. 1990" written by Yasuhiro, et al., entitled "A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode", and in pages 1556 to 1561 of a paper "lEEE journal of solid-state circuits, vol.26, Nov. 1991" written by Katsuyuki, et at., entitled "A 4-Mb pseudo SRAM operating at 2.6.+-.1 V with 3 .mu.A data retention current".
Since data stored in a memory cell of the DRAM disappears, i.e. discharges with the lapse of time, the data of memory cell data must be periodically recharged, which is commonly referred to as a refresh operation. Such a refresh operation is typically executed by a DRAM controller, which is divided into ROR refresh, hidden refresh, CBR(CAS before RAS) refresh, and extended CBR refresh operations in accordance with the performance manner. Recently, a self-refresh operation which extends the extended CBR refresh operation is widely used. The self-refresh operation reduces to a maximum extent the power consumption in the DRAM device to extend the operating time of the computer system using a battery. If not using the DRAM, that is in case where an access to the DRAM is not performed for a long time, the self-refresh operation suppresses to a maximum extent the operation of the DRAM to reduce the power consumption of the DRAM. For example, if a user using a laptop computer for word processing work in an airport is to fly to another place, since a constant level of power is not supplied to the computer, the computer used on boarding should be operable for a long time without interruption by the battery installed therein. A very important concern is not the processing speed of the computer, but the extension of time available for use of the computer by suppressing power consumption. That is, it is important how long the usage time of the computer can be extended without loss of data stored in the DRAM. Further, in other systems, and particularly, when the DRAM is not accessed, the reduction of the power consumption by the DRAM is very important.
The self-refresh operation typically used in the refresh operation of DRAM is executed in the following manner. Generally, a self-refresh input signal is made up of combination of a CBR and a timer output. When a CBR cycle is set up, a normal operation is halted and a refresh mode begins. Here, word line selection is sequentially made not by an external address but by a counter installed in the interior of a chip. Further, a data output operation to the exterior of the chip is not performed and only a cell data restoring operation in the interior of the chip is performed. The difference between the CBR refresh operation and the ROR refresh operation as mentioned above is in the ROR refresh operation, the word line selection is made by the address given by a controller, but in the CBR refresh operation, only a CBR refresh input signal is received from the controller and remaining operations are executed by an on-chip internal circuit. Compared with the ROR refresh operation, the CBR refresh operation has the advantage of lessening the burden of the controller. A latch operation of a row address for selecting a word line is executed by a toggling of a row address strobe signal RAS.
FIG. 1 is a timing diagram showing execution of the CBR refresh operation. Upon input of CBR, a first row address latch is determined by the output of a counter within the chip, and the next row address latch is executed by an activation input of the signal RAS. In such a manner as mentioned above, the refresh operation for every memory cells within the chip is completed.
In case of the self-refresh operation, the refresh operation is executed in the manner of adding the CBR refresh to a timer. In other words, after the refresh mode is started by the CBR cycle, if the toggling of the signal RAS is not executed during a given time period (150 .mu.s), a signal informs the self-refresh input is generated the self-refresh mode is implemented, and a signal that is part of the RAS chain occurs by a first CBR cycle is thereby disabled and the refresh operation is performed by an internal self-refresh circuit. The main distinction between the CBR and self-refresh operations lies in that the self-refresh operation is capable of controlling a refresh period in accordance with the characteristic of each DRAM device. That is, after the self-refresh mode begins and each word line is enabled, the refresh period of memory cell is determined by an oscillator having variable periods within the chip. As well known in the art, the refresh period of the DRAM device is determined by JEDEC which defines a semiconductor size standardization. For example, in case of 4 M DRAM device, the refresh specification therefore is determined as 1K cycle/16 ms. Every 1K/16 ms =1/15.625 .mu.s, i.e. at least 15.625 .mu.s, the refresh operation for cell of the DRAM should be carried out. However, data retention time period of a real measured cell is much longer than the time period of 15.625 .mu.s, thereby allowing for a longer self-refresh period. Moreover, although the time period of 15.625 .mu.s is that assigned for the refresh operation of the DRAM, as the current generation DRAM is changed to the new generation, the system itself will endeavor to maintain the time period, one object of which endeavor may lie in compatibility between the current and new generations.
Since the number of arrays to be activated in on-chip increases as the density of the DRAM device increases, many difficulties will be arise in satisfying duty cycles, i.e. 1 cycle /15.625 .mu.s. For instance in the case of a 16 M DRAM device, the refresh specification therefor is determined as 2K/32 ms. If there are 128 memory cells per one bit line, a 2 M memory cell array is refreshed by the toggling of the signal RAS under a folded bit line architecture. In this case, if a bit line capacitance is 250 fF and an operating voltage is 5 volts, the current required for refreshing cell data of arrays becomes 250 fF * 5/2 * 4 * 2K/100 ns=51.2 mA in the cycle time 100 ns, which corresponds to an average current value. If array sensing operation is accomplished within 10 ns, the current required during the cycle time may correspond to 10 times of the current value in the cycle time 100 ns, and in addition thereto, the value of a peak current may become drastically higher. The important factors in determining the value of array current are a bit line capacitance, operational voltage, array activated by refresh cycle, etc. Hence, to reduce an amount of current consumption, adjustment of the cell number per bit line (for example, if the cell number per bit line corresponds not to 128, but to 64, almost half of the bit line capacitance may be reduced) and adjustment for falling the operating voltage (for example, 5 volts fails to 3.3 volts) have been chosen. On the other hand, the operating voltage may be adjusted in accordance with the refresh cycle, for which the cell refresh time is adjusted while maintaining the duty cycle 15.625 .mu.s (for instance, if the cell refresh time is adjusted from 1K/16 ms to 2K/32 ms, since the number of word lines enabled at a time is reduced to be half, upon a normal operation, half of the current consumed by array is reduced). As will be seen from above, an aim of the self-refresh operation is to reduce the operational current by refresh cycle adjustment, i.e. the power consumption. In one self-refresh application after cell data retention time of a corresponding DRAM device is measured, the self-refresh period is then determined. Here, assuming that the refresh period is 1K cycle/16 ms during the normal operation of the DRAM device and the measured cell data retention time is one second, the self-refresh period becomes 1 s/1024=976.5 .mu.s. That is, since during the normal operation the self-refresh operation is executed every 15.625 .mu.s, but once the self-refresh mode begins, is executed every 976.5 .mu.s, the power consumption by array become reduced as low as 976.5/15.625=62.5 times or so. The self-refresh period is made by using a laser fuse once in in a wafer state or an electrical fuse a package state. Consequently, one of main aims of the self-refresh operation is to extend operational life of a battery by minimizing DRAM operation to an extent capable of maintaining cell data when the DRAM device is not accessed during a preset time period.
The components of power consumed during the operation of DRAM device can be divided into firstly, a DC current component constantly consumed irrespective of an activation state or stand-by state, secondly an, array current component consumed in an array portion such as bit line capacitance charging and discharging, and thirdly, a peripheral circuit current component consumed in driving the DRAM device. In the self-refresh mode, as mentioned above, the power consumption in the DRAM device is reduced by lengthening the self-refresh operation period.
FIG. 2 is a graphical illustration comparing density according to DRAM devices with current consumed by a self-refresh operation. Here, a first line indicates the DC current, and a second line indicates a total self-refresh current in case where the self-refresh period as 125 .mu.s corresponds to 8 times or so of the normal operation. As the density of the DRAM device increases, however, there is a problem in determining the self-refresh period, because the self-refresh period can not increase at a rate of a current self-refresh period. For instance, assuming that the self-refresh operation has a cell data refresh period of 8 times as many periods as the normal operation has. In a 4 M DRAM device, as a normal operation period is 16 ms, the self-refresh period becomes 128 ms, and in 16 M DRAM device, as the normal operation period is 32 ms or 64 ms, the self-refresh period becomes 256 ms or 512 ms. In 64 M DRAM device, as the normal operation period is 64 ms or 128 ms, the self-refresh period becomes 512 s or 1 s, and in 256 M DRAM device, as the normal operation period is 128 or 256 ms, the self-refresh period becomes 1 s or 2 s. It can be expected from such increasing periods that the self-refresh periods do not increase in proportion to each other.
The real size of a memory cell is very tiny as the density of the DRAM device increases, and the operating voltage in view of power consumption and device reliability becomes lower as the number of arrays activated at a time increases. Since the total amount of charge stored in the memory cell is small, the cell data retention time gets increasingly shortened as the density of the DRAM device increases. Therefore, in the 256 M DRAM device, it is almost impossible to expect that the self-refresh period is 2 s and that the self-refresh period has the same 256 ms as the normal operation period in accordance with the cell size and operating voltage. Consequently, technology on conventional DRAM devices has a difficulty in reducing the self-refresh current in the DRAMS having a memory cell density of more than 64 M.
As discussed above, the self-refresh current components are divided the DC, array and peripheral circuit components. The DC current component is always consumed by TTL input buffer such as the signals RAS and CAS, and an internal bias generating circuit irrespective of the activation of device or waiting state, the array current component is consumed by the charging/discharging of the bit line capacitance, and the peripheral circuit current component is consumed by the peripheral circuit for driving the DRAM device, which component is originated from the DC current produced when each internal node is charged/discharged and each signal is changed during operation of the peripheral circuit. An internal signal line is lengthened as the size of the DRAM device is large and as a result, the capacitance to be charged/discharged in the signal line increases and the density of DRAM increases, so the current component according to the operation of the peripheral circuit becomes larger. FIG. 2 shows such an increment state. As the density of the DRAM increases, the peripheral circuit current component is accordingly augmented. In the 256 M DRAM device, the peripheral circuit current component occupies the almost half of the total self-refresh currents. (in FIG. 2, third and fourth lines represent the peripheral circuit current component of the total self-refresh current and the total self-refresh current, respectively).